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MTL007
SXGA Flat Panel Controller
GENERAL DESCRIPTION The MTL007 Flat Panel Display (FPD) Controller is a low-cost input format converter for TFT-LCD Monitor or LCD TV application which accepts 15-pin D-sub RGB graphic signals (through ADC), YUV signals from digital video decoder or digital RGB graphic signals from PanelLink TMDS receiver. It includes a RGB/YUV input processor, video scaling up processor, OSD input interface and output display processor in 128-pin PQFP. interlaced video input. * Glue-less connection to Philips SAA711x digital video decoder. * Built-in YUV to RGB color space converter. * Compliant with digital LVDS/PanelLink TMDS input interface. * PC input resolution up to SXGA 1280x1024 @ 75Hz. Video Processor * Independent programmable Horizontal and Vertical scaling up ratios from 1 to 32 * Flexible de-interlacing unit for digital YUV video input data. * Zoom to full screen resolution of de-interlaced YUV video data stream. * Built-in programmable gain control for white balance alignments. * Built-in programmable 10-bit gamma correction table. * Built-in programmable temporal color dithering. * Built-in programmable interpolation look-up table. * Built-in programmable sharpening & smoothing filters for edge enhancement. * Support smooth panning under viewing window change. Output Processor * Dual pixel (36/48-bit) per clock digital RGB output. * Built-in output timing generator with programmable clock and H/V sync. * Support VGA/SVGA/XGA/SXGA display resolution. * Overlay input interface with external OSD controller. * Double scan capability for interlaced input.
FEATURES General * Auto configuration of sampling clock frequency, phase, H/V center, as well as white balance. * Auto detection of present or non-present or over range sync signals and their polarities. * Composite sync separation and odd/even field detection of interlaced video. * No external memory required. * On-chip output PLL provide clock frequency finetune (inverse, duty cycle and delay). * Serial 2-wire I2C host interface. * Embedded power regulator. * Embedded power on reset circuit. * 3.3V supplier in 128-pin PQFP package. Input Processor * Single RGB (24-bit) input rates up to 135MHz. * Support both non-interlaced and interlaced RGB graphic input signals. * YUV 4:2:2 or YUV 4:1:1 (CCIR601/CCIR656)
Myson Century, Inc. Taiwan: No. 2, Industry East Rd. III, Science-Based Industrial Park, Hsin-Chu, Taiwan Tel: 886-3-5784866 Fax: 886-3-5784349
USA: 4020 Moorpark Avenue Suite 115 San Jose, CA, 95117 Tel: 408-243-8388 Fax: 408-243-3188
sales@myson.com.tw www.myson.com.tw Rev. 1.1 November 2002 page 1 of 65
MTL007
BLOCK DIAGRAM
To external OSD
Digital Video
YUV Input
YUV to RGB
Zoom Buffer
Scale Up
Dithering
OSD & Output Mux
RGB Output
PC RGB
RGB Input Sharpness Gamma Correct
Auto Calibration
Mode Detect
Host Interface
Smooth
Gain Control
Display Timing Generator
To I2C Bus
APPLICATIONS
LVDS/PanelLink TMDS Receiver
Composite/ S-Video
Digital Video Decoder ADC
D-sub RGB graphic signals
MTL007 FPD Monitor Controller
TFT-LCD Flat Panel
MTV230 MCU+OSD
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MTL007
PIN CONNECTION
B2OUT3 B2OUT2 B2OUT1 B2OUT0 G2OUT7 PVDD G2OUT6 PVSS G2OUT5 G2OUT4 G2OUT3 DVSS G2OUT2 DVDD G2OUT1 G2OUT0 R2OUT7 R2OUT6 R2OUT5 R2OUT4 PVSS R2OUT3 R2OUT2 PVDD R2OUT1 R2OUT0 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 DDCLK1 B1OUT7 B1OUT6 B1OUT5 B1OUT4 PVDD B1OUT3P PVSS B1OUT2 B1OUT1 B1OUT0 DVSS G1OUT7 DVDD G1OUT6 G1OUT5 G1OUT4 G1OUT3 G1OUT2 G1OUT1 PVSS G1OUT0 R1OUT7 PVDD R1OUT6 R1OUT5 DVSS R1OUT4 DVDD R1OUT3 R1OUT2 R1OUT1 R1OUT0 PVSS DHSYNC PVDD DVSYNC DDCLK2 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
MTL007 128-pin PQFP
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
B2OUT4 B2OUT5 PVSS B2OUT6 B2OUT7 PVDD DVSS TESTMODE VSYNC HSYNC IPCLK RIN7 RIN6 RIN5 RIN4 RIN3 RIN2 RIN1 RIN0 DVDD GIN7 GIN6 GIN5 GIN4 GIN3 GIN2 GIN1 GIN0 BIN7 BIN6 BIN5 BIN4 BIN3 BIN2 BIN1 BIN0 TDIE DVSS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 DCAP DVDD RAWHS ADVS CLAMP PVSS IRQ PVDD OSDINT OSDEN OSDBLU OSDGRN OSDRED OCLK OHSYNC OVSYNC SCL SDA EXTDCLK1 EXTDCLK2 RSTN AVSS XI XD AVDD DDEN
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MTL007
PIN DESCRIPTION ADC Input Interface (RGB or YUV or TMDS Input Data)
Name IPCLK VSYNC HSYNC/CS RIN[7:0]/YIN[7:0] (RIN[5:0]) GIN[7:0]/UVIN[7:0] (GIN[5:0]) Type I I I I I Pin No. 92 94 93 91-84 (89-84) 82-75 (78-75, 91, 90) Input pixel clock Input Vertical sync Input Horizontal or Composite sync Red or Y channel or TMDS input data (Red channel for 6-bit input) Green or UV channel or TMDS input data (Green channel for 6-bit input) Blue or TMDS input data, or Control bit for YUV video input Bit 4: VPHREF, Video input Horizontal reference signal Bit 3: VPVS, Video input VSYNC signal Bit 2: VPODD, Video input ODD/EVEN field signal Bit 1: VPHS, Video input HSYNC signal Bit 0: VPCLK, Video input clock signal (Blue channel for 6-bit input) Input source HSYNC for measurement TMDS digital input enable Clamp pulse output for ADC Description
BIN[7:0] (BIN[5:0])
I
74-67 (68, 67, 82-79)
RAWHS TDIE CLAMP
I I O
62 66 60
Display Output Interface
Name DDCLK1 DVSYNC OE DHSYNC DDCLK2 R1OUT[0:7] G1OUT[0:7] B1OUT[0:7] R2OUT[0:7] G2OUT[0:7] B2OUT[0:7] O O O O O O O O O O Type Pin No. 1 37 39 35 38 Display output clock Display Vertical sync output Display output enable Display Horizontal sync output Display output clock , bit[7:2] for 6-rlogin rbit panel Description
33-30, 28, 26-25, 23 Red output even data 22, 20-15, 13 11-9, 7, 5-3, 2 128-127, 125-124, 122-119 118,117, 115, 113111, 109,107 106-101, 99-98
Green output even data , bit[7:2] for 6-bit panel Blue output even data Red output odd data , bit[7:2] for 6-bit panel , bit[7:2] for 6-bit panel
Green output odd data , bit[7:2] for 6-bit panel Blue output odd data , bit[7:2] for 6-bit panel
Host Interface
Name RST# SCL Type I I Pin No. 44 48 Description System reset input, active low. Serial bus clock
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MTL007
SDA TESTMODE IRQ I/O I O 47 95 58 Serial bus data Test Mode, Normally grounded. Interrupt request output
OSD Interface
Name OVSYNC OHSYNC OCLK OSDRED OSDGRN OSDBLU OSDEN OSDINT Type O O O I I I I I Pin No. 49 50 51 52 53 54 55 56 Description Vertical sync for external OSD Horizontal sync for external OSD Clock for external OSD OSD red input OSD green input OSD blue input OSD overlay enable OSD intensity
Other Interface
Name XI XO EXTDCLK1 EXTDCLK2 ADVS Type I O I I O Pin No. 42 41 46 45 61 Oscillator frequency input Oscillator frequency output External display clock input 1 External display clock input 2 Vertical sync for A/D converter Description
3.3V Power and Ground
Name DVDD DCAP DVSS PVDD PVSS AVDD AVSS PIN No. 14,29,63,83,116 64 12,27,65,96,114 6,24,36,57,97,108, 126 8,21,34,59,100,110, 123 40 43 Digital power 3.3V External CAP for digital Power Digital ground Pad power 3.3V Pad ground Analog power 3.3V Analog ground Description
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MTL007
FUNCTIONAL DESCRIPTION INPUT PROCESSOR General Description The function of Input Interface is to provide the interface between the MTL007 and external input devices. It can process both non-interlaced and interlaced RGB graphic input, YUV video input, and digital RGB input compliant with digital LVDS/PanelLink TMDS interface. It also contains the built-in YUV to RGB color space converter. i) RGB Input Format
Since the MTL007 is a low cost solution, the RGB input port can only work in Single Pixel mode (24 bits). The R/G/BIN ports are sampled at the rising edge of the RGB input clock.
ii) TMDS Input Format The Digital RGB input port works just in the same way as Sec 3.1.1 except one more input pin is needed: Digital Input Enable DIEN. With a single pixel input interface, the supported format is up to true color, including 18 bit/pixel or 24 bit/pixel. iii) YUV Input Format The YUV input port supports interlaced video data from the most common video decoder ICs like SAA711x. The 16 bit data bus is shared with the ports RIN[7:0] and GIN[7:0]. The 16 bit data is sampled at the rising edge of the shared video clock VPCLK when the shared data enable HREF is active. The supported formats are YUV4:1:1 and YUV4:2:2 with CCIR601/CCIR656 standard. iv) Input HSYNC Path Besides the pin HSYNC, the MTL007 provides another pin RAWHS to support Sync Processor in the MTL007. Generally, the HSYNC generated by an ADC may have a very narrow pulse width and a different polarity from the original HSYNC provided by the source. The RAWHS input provides the path of original HSYNC connection to the MTL007, which makes Sync Processor in the MTL007 work correctly. v) YUV to RGB Converter It is used to convert YCbCr format into RGB format. The basic equations are as follows: R = Y + 1.371(Cr - 128) G = Y - 0.698(Cr - 128) - 0.336(Cb - 128) B = Y + 1.732(Cb - 128) vi) De-interlace mode For interlace input, the MTL007 features de-interlacing algorithm for processing interlaced video data.In this mode, two fields are toggled displayed. The missing lines are calculated from interpolating the neighbor lines. This algorithm has an average good quality for still and moving picture.
vii) Sync Processor The V/H SYNC processing block performs the functions of Composite signal separation/insertion, SYNC inputs presence check, frequency counting, polarity detection and control. It contains a de-glitch circuit to filter out any pulse shorter than one OSC period treated as noise on V/H SYNC pulses.
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MTL007
V/H SYNC Frequency Counter The MTL007 can measure VSYNC/HSYNC frequency counted in proper clock and save the information in registers. Users can read out them to calculate VSYNC/HSYNC frequency as following formulas: fvsync = fosc / Nvsync 1/256 fhsync = fosc / Nhsync 8 ,Where fvsync fhsync fosc Nvsync Nhsync : VSYNC frequency : HSYNC frequency : oscillator clock with 14.31818 MHz : counted number of VSYNC : counted number of HSYNC
V/H SYNC Presence Check This function checks the input VSYNC, where Vpre flag is set when VSYNC is over 40Hz or cleared when VSYNC is under 10Hz, and the input HSYNC, where Hpre flag is set when HSYNC is over 10Khz or cleared when HSYNC is under 10Hz. V/H Polarity Detect This function detects the input VSYNC/HSYNC high and low pulse duty cycles. If the high pulse duration is longer than that of the low pulse, the negative polarity is asserted; otherwise, positive polarity is asserted. Composite SYNC separation/insertion The MTL007 continuously monitors the input HSYNC. If the input VSYNC can be extracted from it, a CVpre flag is set. The MTL007 can insert HSYNC pulse during Composite VSYNC's active time and the insertion frequency can adapt to original HSYNC's.
viii) Auto Tune Auto Tune function consists of Auto Position automatically centering the screen and Auto Calibration containing Phase Calibration, Histogram, Min/Max Value, and Pixel Grab described as below. With this auto adjustment support, it is possible to measure the correct phase, frequency, gain, and offset of ADC. The horizontal and vertical back porches of input image and the horizontal and vertical active regions can also be measured. Firmware can adjust input image registers automatically by reading Auto Tune's registers in single or burst mode. Auto Position The MTL007 provides Horizontal/Vertical back porch and active region values. Users can use these values to set input sample registers to aid in centering the screen automatically. Phase Calibration The MTL007 provides Auto Calibration registers to measure the quality of current ADC's phase and frequency. The biggest Auto Calibration registers value means the right value of ADC's phase and frequency. The MTL007 has two kinds of algorithms to calculate Auto Calibration's value. One is traditional Difference method; the other is MYSON's proprietary method. It is suggested to use the latter one for better performance.
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MTL007
Histogram Histogram means the total number of input pixels below/above one threshold value, for individual R, G, B colors. This advanced function helps firmware to analyze ADC performance. Usually Firmware can use this information to measure ADC's noise margin, adjust its offset and gain, or even aid in the mode detection. Min/Max Value Min/Max value means the minimum or maximum pixel value within the specified input active image region for each RGB channel. This information is usually used to adjust ADC's offset and gain. Pixel Grab Pixel Grab means users can grab a single input pixel at any one point. The position of the point can be programmed by users. This is another traditional method to measure ADC's phase and frequency.
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MTL007
VIDEO PROCESSOR General Description The MTL007 possesses a powerful and programmable video processor by providing the following functions: Scaling Up/Down, Edge Enhancement (Sharpness & Smooth Control), Gain Control, Brightness Control, Gamma Gamma Correction, and Dithering Control. The block diagram of Video Processor is as follows:
FLIP
Scaling Factor Interpolation Table
SCALING
SHARPNESS
Sharpness Factor
SMOOTH
GAIN
Gain Factor
BRIGHTNESS
Brightness Factor
GAMMA
Gamma Table
DITHERING
Dithering Table
Figure-1
Video Processor Block Diagram
i)
Scaling
The MTL007 provides scaling function up ranging from 1 to 32, and for both horizontal and vertical processing. For scaling up, both horizontal and vertical processing, the MTL007 provides four methods: Pass Mode: Image will be passed through without considering any scaling factor. Duplicate Mode: Image will be scaled up based on scaling factor. Every point of output image comes from the input. By this method, Output image will have a good contrast but may be non-uniformed. Bilinear Mode: Image will be scaled up based on scaling factor. Every point of output image data will be filtered by bilinear filter. By this method, output image will have a good scaling quality but may be blurred. Interpolation Table Mode: Image will be scaled up based on scaling factor. Every point of output image data will be filtered by user-defined filter.
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MTL007
A B
Input pixel
O Interpolation pixel SC 64 SC' [a]
63
32 [b] [c] 32
[a] : duplicate filter [b] : bilinear filter [c] : user defined filter O = [(64-SC')*A+SC'*B]/64 63 SC'
Figure-2
Scaling filter
ii) Edge Enhancement The MTL007 uses a 5x1 Sharpening filter and a 5x1 Smoothing filter to improve edge effect. The coefficients of latter are fixed, but the other are programmable with eight steps. iii) Gain/Brightness Control The MTL007 provides Gain and Brightness control to adjust the contrast and brightness of output color by programming gain and brightness coefficients. This adjustment is applied to RGB colors individually. Auto-white balance is possible by using this function. iv) Gamma Correction Gamma Correction is used to compensate the non-linearity of LCD display panel. The MTL007 contains an 8-bit Gamma table to fix this phenomenon. v) Color Dithering The MTL007 supports true color (8 bits per color) or high color (6 bits per color) display. In the latter case, users can turn on dithering function to avoid artificial contour due to truncation. For dithering, it supports two methods: Static dithering: Dithering coefficient is fixed. Temporal dithering: Dithering coefficient will change by time.
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MTL007
OUTPUT PROCESSOR General Description Output processor provides the interface for both LCD panel and OSD controller. Output frame rate must be equal to input frame rate and output display time must be equal to input display time, because of no frame buffer. i) Display Timing Generation Output frame rate is equal to input frame and external frame buffer is not needed.
Input Frame X
Output Frame
X: lock position Figure-3 Display Timing modes
ii) OSD Overlay The MTL007 allows the integration of overlay data with the scaled output pixel stream. It provides a fully compatible OSD interface. Individual OSD clock, OSD HSYNC and OSD VSYNC are sent to external OSD device. The MTL007 receives OSD Enable, OSD intensity, OSD Red, OSD Green, and OSD Blue from external OSD device. Another MTL007 provides OSD overlay-transparent function in two modes, each has 16 steps by programming weight factors. iii) RGB Output Format The MTL007 output interface consists of two pixel ports, each containing Red, Green, and Blue color information with a resolution of 6/8 bits per color. These two ports are mapped to PORT1 and PORT2. The control signals for output port are display horizontal sync signal (DHSYNC), display vertical sync signal (DVSYNC) and display data enable signal (DDEN). All the signals mentioned above are synchronous to the output clock. The output timing relative to the active edge of the output clock is programmable. There are RGB output formats: Dual Pixel Mode It is designed to support TFT panels with dual pixel input. PORT1 and PORT2 are used. The first pixel is at PORT1, and the second at PORT2.
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MTL007
DCLK1 DCLK2 DDEN R1OUT/ G1OUT/ B1OUT R2OUT/ G2OUT/ B2OUT
000 000
rgb0
rgb2
rgb4
rgb6
rgb8
rgb1
rgb3
rgb5
rgb7
rgb9
Figure-4
Display Data Timing
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MTL007
HOST INTERFACE General Description The main function of Host Interface is to provide the interface between the MTL007 and external CPU by 2-wire I2C Bus. It can generate all the I/O decoded control timing to control all the registers in the MTL007.
i)
I2C Serial Bus
The I2C serial interface use 2 wires, SCK (clock) and SDA(data I/O). The SCK is used as the sampling clock and SDA is a bi-directional signal for data. The communication must be started with a valid START condition, concluded with STOP condition and acknowledged with ACK condition by receiver. The I2C bus device address of the MTL007 is 0111010x. SCK, serial bus clock. SDA, bi-directional serial bus data. The START condition means a HIGH to LOW transition of SDA when SCK is high, the STOP condition means a LOW to HIGH transition of SDA when SCK is high. And data of SDA only can change during SCK is low as shown in Figure-5.
SDA
SCK
START
DATA CHANGE
DATA CHANGE
STOP
Figure-5
START, STOP and DATA definition
The I2C interface supports Random Write, Sequential Write, Current Address Read, Random Read and Sequential Read operations. Random Write For Random Write operation, it contains the slave address with R/W bit set to 0 and the word address that is comprised of eight bits and provides the access to any one of 256 bytes in the selected memory range. Upon receipt of the word address, the MTL007 responds with an Acknowledge, waits for the data bits again responding an Acknowledge, and then the master generates a stop condition as shown in Figure-6.
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MTL007
S T A R T SDA WA C K A C K A C K S T O P
SLAVE ADDRESS
WORD ADDRESS
DATA
Figure-6
Random Write
Sequential Write The initial step of Sequential Write is the same as Random Write, after the receipt of each word data, the MTL007 will respond with an Acknowledge and then internal address counter will increment by one for the next data write. If the master would stop writing data, it generates a stop condition as shown in Figure-7.
S T A R SLAVE T ADDRESS SDA WA C K A C K A C K A C K A C K S T O P
WORD ADDRESS
DATA n
DATA n+1
DATA n+x
Figure-7 Current Address Read
Sequential Write
The MTL007 contains an address counter which maintains the last access address incremented by one. If the last access address is n, the read data should access from address n+1. Upon receipt of the slave address with R/W bit set to 1, the MTL007 generates an Acknowledge and transmits eight bits data. After receiving data the master will generate a stop condition instead of an Acknowledge as shown in Figure-8.
S T A R T SDA WA C K
SLAVE ADDRESS
DATA
S T O P
Figure-8
Current Address Read
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MTL007
Random Read The operation of Random Read allows access to any address. Before reading data operation, it must issue a "dummy write" operation -- a start condition, slave address and then the word address for read. After responding the word address acknowledge, the master generates a start condition again and slave address with R/W bit is set to 1. The MTL007 then transmits the 8 bits of data. Upon the completion of receiving data, the master will generate a stop condition instead of an Acknowledge as shown in Figure-9.
S T A R SLAVE T ADDRESS SDA WA C K A C K RA C K S T A R T
WORD ADDRESS
SLAVE ADDRESS
DATA
S T O P
Figure-9 Sequential Read
Random Read
The initial step can be as either Current Address Read or Random Read. The first read data is transmitted the same manner as other read methods. However, the master generates an Acknowledge indicating that it requires more data to read. The MTL007 continues to output data for each Acknowledge received. The output data is sequential and the internal address counter increments by one for next read data as shown in Figure-10.
S T A R T SDA RA C K A C K A C K
SLAVE ADDRESS
DATA n
DATA n+1
DATA n+x
S T O P
Figure-10 Sequential Read
ii) Interrupt The MTL007 supports one interrupt output signal (IRQ) which can be programmed to provide SYNC related or function status related interrupts to the system. Upon receiving the interrupt request, Firmware needs to first check the interrupt event by reading the Interrupt Flag Control registers (Reg. E8h and E9h) to decide what events are happening. After the operation is finished, Firmware needs to clear interrupt status by writing the same registers Reg. E8h and E9h. Furthermore, by using the Interrupt Flag Enable registers (Reg. EAh and EBh), each interrupt event can be masked.
iii) Update Register Contents
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MTL007
I/O write operation to some consecutive register sets can have the "Double Buffer" effect by setting the Reg. C1h/D4. Written data is first stored in an intermediate bank of latches and then transferred to the active register set by setting Reg. C1h/D1-0.
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MTL007
ON-CHIP PLL General Description The MTL007 needs two clock sources to drive synchronous circuits on chip. These clocks are generated from the internal Phase Lock Loop (PLL) circuits with reference to the oscillator clock which is applied to pin XI and XO by an external quartz crystal at 14.31818 MHz. The first one is the same as to the oscillator clock at frequency (14.31818 MHz) to detect and measure graphic vertical and horizontal SYNC Frequency, Polarity as well as Presence. The second is the display clock for display controller on chip and output signals to LCD panel.
i)
Reference Clock
It is the counting basis of counter values in SYNC Processor such as VS and HS period count registers; that is, the read back values from these registers must multiply the period of this clock to estimate VS and HS frequency. Incorporating with polarity and frequency information of VS and HS, it can show the input graphic image mode and pixel clock frequency.
ii) Display Clock This clock is the synchronous clock for LCD panel. According to the LCD panel resolution of applications, the display clock range is from 50 MHz to 200 MHz by means of choosing a set of appropriate values for M, N as well as R. The formula to calculate the desired frequency of display clock is as follows: fmclk = fosc(M+1)/(N+1)1/R Where fmclk fosc M N R : the desired display clock : oscillator clock with 14.31818 MHz : post-divider ratio : pre-divider ratio : optional divider ratio
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MTL007
REGISTER DESCRIPTION Input Control Register
Address 00h 01h 02h 03h Mode R/W R/W R/W R/W Registers Input Image Vertical Active Line Start - Low Input Image Vertical Active Line Start - High Input Image Vertical Active Lines - Low Input Image Vertical Active Lines - High Reset value 00h 00h 00h 00h
04h 05h 06h 07h
R/W R/W R/W R/W
Input Image Horizontal Active Pixel Start - Low Input Image Horizontal Active Pixel Start - High Input Image Horizontal Active Pixels - Low Input Image Horizontal Active Pixels - High
00h 00h 00h 00h
10h 11h 12h 13h 14h 15h 16h * 17h * 18h * 19h 1Ah 1Ch 1Dh * 1Eh 1Fh 20h 21h
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO R/W R/W
Input Image Control Register 0 Input Image Control Register 1 Input Image Control Register 2 Input Image Control Register 3 Input Image Control Register 4 Input Image Control Register 5 Input Image Control Register 6 Input Invert Control Input Delay Control 0 Input Delay Control 1 Input Delay Control 2 HS1 Sample Window Forward Extend HS1 Sample Window Backward Extend Input Miscellaneous Control Input Image Status Register Input Image Back Porch Guard Band Input Image Front Porch Guard Band
00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
Frame Sync Registers
Address * 28h * 29h Mode R/W R/W Frame Sync Control NFB Display VSYNC Control Registers Reset value 00h 00h
2Ch
R/W
Input Image Vertical Lock Position - Low
00h
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MTL007
2Dh 2Eh 2Fh R/W R/W R/W Input Image Vertical Lock Position - High Input Image Horizontal Lock Position - Low Input Image Horizontal Lock Position - High 00h 00h 00h
Auto Calibration Registers
Address 30h 31h Mode R/W R/W Auto Calibration Control 0 Auto Calibration Control 1 Registers Reset value 80h 00h
34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh
RO RO RO RO RO RO RO RO RO RO RO RO
Auto Calibration RED Value - Byte 0 Auto Calibration RED Value - Byte 1 Auto Calibration RED Value - Byte 2 Auto Calibration RED Value - Byte 3 Auto Calibration GREEN Value - Byte 0 Auto Calibration GREEN Value - Byte 1 Auto Calibration GREEN Value - Byte 2 Auto Calibration GREEN Value - Byte 3 Auto Calibration BLUE Value - Byte 0 Auto Calibration BLUE Value - Byte 1 Auto Calibration BLUE Value - Byte 2 Auto Calibration BLUE Value - Byte 3
-
40h 41h 42h 43h 44h 45h 46h
R/W R/W R/W R/W R/W R/W R/W
Pixel Grab V Reference Position - Low Pixel Grab V Reference Position - High Pixel Grab H Reference Position - Low Pixel Grab H Reference Position - High Histogram Reference Color - RED Histogram Reference Color - GREEN Histogram Reference Color - BLUE
00h 00h 00h 00h 00h 00h 00h
Sync Processor Registers
Address 48h 49h Mode R/W R/W SYNC Processor Control Auto Position Control Registers Reset value 00h 00h
4Ah 4Bh 4Ch
R/W R/W R/W
Auto Position Reference Color - RED Auto Position Reference Color - GREEN Auto Position Reference Color - BLUE
00h 00h 00h
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MTL007
4Eh 4Fh R/W R/W Clamp Pulse Control 0 Clamp Pulse Control 1 00h 00h
50h 51h 52h 53h 54h 55h 56h 57h
RO RO RO RO RO RO RO RO
Input VS Period Count by REFCLK - Low Input VS Period Count by REFCLK - High Input V Back Porch Count by Input HS - Low Input V Back Porch Count by Input HS - High Input V Active Lines Count by Input HS - Low Input V Active Lines Count by Input HS - High Input V Total Lines Count by Input HS - Low Input V Total Lines Count by Input HS - High
-
58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh
RO RO RO RO RO RO RO RO
Input HS Period Count by REFCLK - Low Input HS Period Count by REFCLK - High Input H Back Porch Count by Input Pixel Clock - Low Input H Back Porch Count by Input Pixel Clock - High Input H Active Pixels Count by Input Pixel Clock - Low Input H Active Pixels Count by Input Pixel Clock - High Input H Total Pixels Count by Input Pixel Clock - Low Input H Total Pixels Count by Input Pixel Clock - High
-
Display Control Registers
Address 60h 61h 62h 63h 64h 65h 66h 67h * 68h * 69h * 6Ah * 6Bh Mode R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Display Vertical Total - Low Display Vertical Total - High Display Vertical SYNC End- Low Display Vertical SYNC End - High Display Vertical Active Start - Low Display Vertical Active Start - High Display Vertical Active End - Low Display Vertical Active End - High Display Vertical Border Start - Low Display Vertical Border Start - High Display Vertical Border End - Low Display Vertical Border End - High Registers Reset value 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
70h
R/W
Display Horizontal Total - Low
00h
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MTL007
71h 72h 73h 74h 75h 76h 77h * 78h * 79h * 7Ah * 7Bh R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Display Horizontal Total - High Display Horizontal SYNC End - Low Display Horizontal SYNC End - High Display Horizontal Active Start - Low Display Horizontal Active Start - High Display Horizontal Active End - Low Display Horizontal Active End - High Display Horizontal Border Start - Low Display Horizontal Border Start - High Display Horizontal Border End - Low Display Horizontal Border End - High 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
* 7Eh 7Fh
R/W R/W
NFB Timing Load Value NFB Timing Control
00h 60h
88h 89h 8Ah
R/W R/W R/W
Output Image Control Register 0 Output Image Control Register 1 Output Image Control Register 2
00h 00h 00h
90h 91h 92h 93h 94h 95h * 96h * 97h * 98h
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Color Gain Control - RED Color Gain Control - GREEN Color Gain Control - BLUE Brightness Control - RED Brightness Control - GREEN Brightness Control - BLUE Border Window Color - RED Border Window Color - GREEN Border Window Color - BLUE
80h 80h 80h 00h 00h 00h 00h 00h 00h
* 9Eh 9Fh
R/W R/W
Dithering Register Gamma Table Data Port
-
A0h A1h A2h A3h A4h A5h
R/W R/W R/W R/W R/W R/W
OSD Control Register 0 OSD Control Register 1 OSD Control Register 2 OSD Control Register 3 Output Invert Control Output Tri-State Control
08h 00h 00h 00h 00h 00h
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A6h A7h * A8h A9h AAh ABh ACh ADh AEh AFh R/W R/W R/W R/W R/W R/W RO RO RO RO Output Clocks Delay Adjustment Output Clocks Duty Cycle Adjustment Display Line Buffer Data Sample Adjustment Output Miscellaneous Control Output Vertical Active Line Number - Low Output Vertical Active Line Number - High Output Horizontal Total Pixel Number - Low Output Horizontal Total Pixel Number - High Output Horizontal Total Residue Number - Low Output Horizontal Total Residue Number - High 00h 00h 00h 00h FFh 02h -
Zoom Control Register
Address B0h B1h Mode R/W R/W Zoom Control Register 0 Zoom Control Register 1 Registers Reset value 00h 00h
B4h B5h B6h B7h
R/W R/W R/W R/W
Zoom Vertical Scale Ratio - Low Zoom Vertical Scale Ratio - High Zoom Horizontal Scale Ratio - Low Zoom Horizontal Scale Ratio - High
00h 00h 00h 00h
BFh
R/W
Interpolation Table Data Port
-
Host Control Register
Address C1h * C6h * C7h * C8h CBh Mode R/W R/W R/W R/W RO Host Control Register 1 Host Fill Color - RED Host Fill Color - GREEN Host Fill Color - BLUE Host Access Mode Status Registers Reset value 00h 00h 00h 00h -
Clock Control Registers
Address E0h Mode R/W Clock Control Register Registers Reset value 00h
E1h E2h E3h
WO R/W R/W
Clock Synthesizer Value Load Clock Synthesizer N Value Clock Synthesizer M Value
0Bh 32h page 22 of 65
MTL007
E6h R/W Clock Synthesizer R Value 00h
Interrupt Control Registers
Address E8h E9h EAh EBh ECh Mode R/W R/W R/W R/W R/W SYNC Interrupt Flag Control General Interrupt Flag Control SYNC Interrupt Enable Control General Interrupt Enable Control HS Frequency Change interrupt Compare Registers Reset value 00h 00h 00h 00h 00h
Miscellaneous Registers
Address * F0h F1h Mode RO R/W Device/Revision ID Power Management Control Registers Reset value 10h 00h
* F8h * F9h * FAh
R/W RO R/W
Line Buffer Self Test Control Line Buffer Self Test Result Status Debug/Test Mode Control
02h 00h
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Input Image Vertical Active Line Start - Low (Address 00h) (R/W) It defines the low byte of the start position of the Vertical Active Window. D7-0 IV_ACT_START[7:0]
Input Image Vertical Active Line Start - High (Address 01h) (R/W) It defines the high byte of the start position of the Vertical Active Window. D7-3 D2-0 Reserved IV_ACT_START[10:8]
Input Image Vertical Active Lines - Low (Address 02h) (R/W) It defines the low byte of the number of active lines of the Vertical Active Window. D7-0 IV_ACT_LEN[7:0]
Input Image Vertical Active Lines - High (Address 03h) (R/W) It defines the high byte of the number of active lines of the Vertical Active Window. D7-3 D2-0 Reserved IV_ACT_LEN[10:8]
Input Image Horizontal Active Pixel Start - Low (Address 04h) (R/W) It defines the low byte of the start position of the Horizontal Active Window. D7-0 IH_ACT_START[7:0]
Input Image Horizontal Active Pixel Start - High (Address 05h) (R/W) It defines the high byte of the start position of the Horizontal Active Window. D7-3 D2-0 Reserved IH_ACT_START[10:8]
Input Image Horizontal Active Pixels - Low (Address 06h) (R/W) It defines the low byte of the number of active pixels of the Horizontal Active Window. D7-0 IH_ACT_WIDTH[7:0]
Input Image Horizontal Active Pixels - High (Address 07h) (R/W) It defines the high byte of the number of active pixels of the Horizontal Active Window. D7-3 D2-0 Reserved IH_ACT_WIDTH[10:8]
Input Image Control Register 0 (Address 10h) (R/W)
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D7 Horizontal Sampling Point Reference 0: from Input HSYNC; 1: from Input HREF (only for Video Decoder) Input YCBCR Format 0: 4-2-2 1: 4-1-1 Digital RGB 6 bit Mode 0: 8 bits; 1: 6 bits Digital RGB Mode Select 0: RGB Input from ADC; 1: RGB Input from Panel Link Input Image Format 0: RGB888; 1: YCBCR Reserved Input Image Source 0: from Graphic source through ADC; 1: from Video source through Video Decoder like SAA7111A Reserved
D6
D5
D4
D3
D2 D1
D0
Input Image Control Register 1 (Address 11h) (R/W) D7-4 D3 Reserved CCIR656 mode Enable 0: Disable; 1: Enable CCIR656 VDE Select 0: from Internal Programming; 1: from Internal Self-Decode Reserved
D2
D1-0
Input Image Control Register 2 (Address 12h) (R/W) D7 Input ODD Field Invert 0: Normal; 1: Invert External Input Interlace Select 0: Non-interlace; 1: Interlace External Input VSYNC Polarity 0: Active Low; 1: Active High External Input HSYNC Polarity 0: Active Low;
page 25 of 65
D6
D5
D4
MTL007
1: Active High D3 Input ODD Field Source 0: from Internal Detection; 1: from External pin Input Interlace Source 0: from Internal detection; 1: from Register setting (D6) Input VSYNC Polarity Source 0: from Internal detection; 1: from Register setting (D5) Input HSYNC Polarity Source 0: from Internal detection; 1: from Register setting (D4)
D2
D1
D0
Input Image Control Register 3 (Address 13h) (R/W) D7 Active Position Area for Auto Position in TMDS 0: from Internal Detection; 1: from External Data Enable (TDIE) Data Enable (TDIE) Delay in TMDS 000: No delay; 001: +3 clocks delay; 010: -3 clocks delay; 011: Reserved; 100: +1 clock delay; 101: +2 clocks delay; 110: -2 clocks delay; 111: -1 clock delay Reserved Input Vertical Timing based on VSYNC 0: Leading Edge; 1: Trailing Edge Input Horizontal Timing based on HSYNC 0: Leading Edge; 1: Trailing Edge
*D6-4
D3-2 D1
D0
Input Image Control Register 4 (Address 14h) (R/W) D7 Input ODD Field Detection Point 0: at the start of VSYNC pulse; 1: at the end of VSYNC pulse Reserved Input Image CBCR Order Swap 0: Normal; 1: Swap Reserved
page 26 of 65
D6-5 D4
D3
MTL007
*D2 Input HSYNC Pulse Cut 0: Normal; 1: Cut Short Input HSYNC Pulse Input H/V SYNC Sample Mode 00: Filtered by a de_bounced filter; 01: Sampled by REFCLK to SYNC Processor, sampled by IDCLK to others; 1x: Pass Through
*D1-0
Input Image Control Register 5 (Address 15h) (R/W) D7 Horizontal Pixel Valid Select 0: from Internal Programming; 1: from External HREF Reserved External Display Enable Select 0: Disable; 1: Enable Reserved Input Clock IDCLK Mode 0: Internal IDCLK can only tune Invert; 1: Internal IDCLK can tune Invert, Delay and Duty cycles Pixclk1 Adjustment Enable. Input Sample Clock ADCCLK1 Mode 0: Internal ADCCLK1 can only tune Invert; 1: Internal ADCCLK1 can tune Invert, Delay and Duty cycles
D6 D5
D4-3 *D2
*D1 *D0
Input Image Control Register 6 (Address 16h) (R/W) D7 Input Rin-ports and Bin-ports Swap 0: Normal; 1: Swap Bit Order in Port A0: Normal; 1: Reverse Flush Line Buffer Enable 0: Disable; 1: Enable Reserved ADC HS Polarity when D1=1 0: Active Low; 1: Active High Raw HS path Enable 0: Disable; 1: Enable Reserved
page 27 of 65
D6
*D5
D4-3 D2
D1
D0
MTL007
*Input Invert Control (Address 17h) (R/W) D7 *D6 Reserved Internal ADCCLK1 Tuning 0: Disable; 1: Enable Input VSYNC Invert 0: Normal; 1: Invert Input HSYNC Invert 0: Normal; 1: Invert Reserved Input Clock IDCLK Invert 0: Normal; 1: Invert Reserved Input Sample Clock ADCCLK1 from PC GRAPHIC Invert 0: Normal; 1: Invert
D5
D4
D3 D2
D1 *D0
*Input Delay Control 0 (Address 18h) (R/W) D7-4 Reserved
*D3-0 Input Clock IDCLK Delay Adjustment 16 steps to change, each of them is 1ns delay/step.
*Input Delay Control 1 (Address 19h) (R/W) *D7-6 *D5-4 *D3-0 Input Pixel Delay Adjustment 4 steps to adjust, Typical 0.2ns/step External Data Enable Delay Adjustment 4 steps to adjust, Typical 0.2ns/step Input Sample Clock ADCCLK1 Delay Adjustment 16 steps to change, each of them is 1ns delay/step
*Input Delay Control 2 (Address 1Ah) (R/W) *D7-4 Input VSYNC Delay Adjustment 1111: 7 IDCLKs delay; 1110: 6 IDCLKs delay; 1101: 5 IDCLKs delay; 1100: 4 IDCLKs delay; 1011: 3 IDCLKs delay;
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1010: 2 IDCLKs delay; 1001: 1 IDCLK delay; 1000: No delay; 0111: 7ns gate delay; 0110: 6ns gate delay; 0101: 5ns gate delay; 0100: 4ns gate delay; 0011: 3ns gate delay; 0010: 2ns gate delay; 0001: 1ns gate delay; 0000: No delay D3-0 Input HSYNC Delay Adjustment 16 steps to change, each of them is 1ns delay/step
Input HS Pulse Width Forward Extend (Address 1Ch) (R/W) D7-0 Input HS Pulse Width Forward Extend by IDCLK HS1FWEXT[7:0]: Used when Interlace First/Second Field Detection.
Input HS Pulse Width Backward Extend (Address 1Dh) (R/W) D7-0 Input HS Pulse Width Backward Extend by IDCLK HS1BWEXT[7:0]: Used when Interlace First/Second Field Detection.
*Input Miscellaneous Control (Address 1Eh) (R/W) D7 *D6-2 *D1 Reserved Internal VIU Debug Bus Select VIU Counter Test Enable 0: Normal; 1: Enable VIU Test Enable 0: Normal; 1: Enable
*D0
Input Image Status Register (Address 1Fh) (RO) D7 D6 D5 Display VSYNC Monitor Show Display VSYNC signal directly. Input VSYNC Monitor Show Input VSYNC signal directly. External Input Interlace Status 0: Non-interlace; 1: Interlace Extracted CVSYNC Present Status 0: Not Present; 1: Present
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D4
MTL007
D3 External Input VSYNC Present Status 0: Not Present; 1: Present External Input HSYNC Present Status 0: Not Present; 1: Present External Input VSYNC Polarity Status 0: Active Low; 1: Active High External Input HSYNC Polarity Status 0: Active Low; 1: Active High
D2
D1
D0
Input Image Back Porch Guard Band (Address 20h) (R/W) D7-0 Input Image Back Porch Guard Band by IDCLK HBPGB[7:0]: Used in Auto Position detection to mask out unwanted data.
Input Image Front Porch Guard Band (Address 21h) (R/W) D7-0 Input Image Front Porch Guard Band by IDCLK HFPGB[7:0]: Used in Auto Position detection to mask out unwanted data.
*Frame Sync Control (Address 28h) (R/W) D7-6 *D5 Reserved Lock Counter Select 0: from STACOUNT; 1: from VALCOUNT Interlace Second Field Shift One line Enable 0: No Shift; 1: Shift One Line Interlace Horizontal Lock Event Select 0: Normal; 1: Only Lock on the First Field Horizontal Lock Event Function ON 0: OFF; 1: ON Reserved
*D4
*D3
*D2
D1-0
*NFB Display VSYNC Control (Address 29h) (R/W) It defines Display VSYNC passed through from Input VSYNC tuning control in NFB mode. D7-5 *D4 Reserved Input VSYNC pass through to Output VSYNC Enable
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0: Disable; 1: Enable D3 *D2-0 Reserved Output VSYNC delay 000: No delay; 001: 1 line delay; 010: 2 lines delay; 011: 3 lines delay; 100: 4 lines delay; 101: 5 lines delay; 110: 6 lines delay; 111: 7 lines delay
Input Image Vertical Lock Position - Low (Address 2Ch) (R/W) It defines the low byte of the number of input lines where Display image timing synchronizes the input image source. D7-0 IPV_LOCK_POS[7:0]
Input Image Vertical Lock Position - High (Address 2Dh) (R/W) It defines the high byte of the number of input lines where Display image timing synchronizes the input image source. D7-3 D2-0 Reserved IPV_LOCK_POS[10:8]
Input Image Horizontal Lock Position - Low (Address 2Eh) (R/W) It defines the low byte of the number of input pixel clocks where Display image timing synchronizes the input image source. D7-0 IPH_LOCK_POS[7:0]
Input Image Horizontal Lock Position - High (Address 2Fh) (R/W) It defines the high byte of the number of input pixel clocks where Display image timing synchronizes the input image source. D7-3 D2-0 Reserved IPH_LOCK_POS[10:8]
Auto Calibration Control 0 (Address 30h) (R/W) D7 Pixel Grab Ready Flag (RO) 0: Ready; 1: Not Ready
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D6 Pixel Grab Update Enable 0: Stop updating; 1: Continue updating Threshold Select Used in Histogram mode or MIN/MAX mode. 0: High bound / MAX; 1: Low bound / MIN Phase Calibration Method Select 0: MYSON proprietary method; 1: Difference Value method Auto Calibration Modes Select The measured value is available one item at a time, selected as shown: 00: Phase Calibration Mode; 01: Histogram Mode; 10: MIN/MAX Mode; 11: Pixel Grab Mode Auto Calibration Burst Mode Enable (except Pixel Grab Mode) 0: Single Mode; 1: Burst Mode Auto Calibration Enable (W) (except Pixel Grab Value) 0: Disable; 1: Enable Auto Calibration Ready Flag (R) 0: Ready; 1: Not Ready
D5
D4
D3-2
D1
D0
Auto Calibration Control 1 (Address 31h) (R/W) *D7 Pixel Grab Select 0: Single Pixel Grab; 1: Dual Pixel Grab Reserved Mask LSBs of Input Image Select 000: No Mask; 001: Mask bit0; 010: Mask bit0,1; 011: Mask bit0,1,2; 100: Mask bit0,1,2,3; 101: Mask bit0,1,2,3,4; 110: Mask bit0,1,2,3,4,5; 111: Mask bit0,1,2,3,4,5,6
D6-3 D2-0
Auto Calibration RED Value - Byte 0 (Address 34h) (RO) It states the byte 0 of the number of Phase Calibration RED value in one frame or the byte 0 of the number of Histogram Red value in one frame or the Pixel Grab RED value in one frame of Non_interlace mode or FIRST field of Interlace mode.
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MTL007
D7-0 CALVAL_R[7:0]
Auto Calibration RED Value - Byte 1 (Address 35h) (RO) It states the byte 1 of the number of Phase Calibration RED value in one frame or the byte 1 of the number of Histogram Red value in one frame or the Pixel Grab GREEN value in one frame of Non_interlace mode or FIRST field of Interlace mode. D7-0 CALVAL_R[15:8]
Auto Calibration RED Value - Byte 2 (Address 36h) (RO) It states the byte 2 of the number of Phase Calibration RED value in one frame or the byte 2 of the number of Histogram Red value in one frame or the Pixel Grab BLUE value in one frame of Non_interlace mode or FIRST field of Interlace mode. D7-0 CALVAL_R[23:16]
Auto Calibration RED Value - Byte 3 (Address 37h) (RO) It states the byte 3 of the number of Phase Calibration RED value in one frame. D7-6 D5-0 Reserved CALVAL_R[29:24]
Auto Calibration GREEN Value - Byte 0 (Address 38h) (RO) It states the byte 0 of the number of Phase Calibration GREEN value in one frame or the byte 0 of the number of Histogram GREEN value in one frame or the Pixel Grab RED value in one frame of Non_interlace mode or SECOND field of Interlace mode. D7-0 CALVAL_G[7:0]
Auto Calibration GREEN Value - Byte 1 (Address 39h) (RO) It states the byte 1 of the number of Phase Calibration GREEN value in one frame or the byte 1 of the number of Histogram GREEN value in one frame or the Pixel Grab GREEN value in one frame of Non_interlace mode or SECOND field of Interlace mode. D7-0 CALVAL_G[15:8]
Auto Calibration GREEN Value - Byte 2 (Address 3Ah) (RO) It states the byte 2 of the number of Phase Calibration GREEN value in one frame or the byte 2 of the number of Histogram GREEN value in one frame or the Pixel Grab BLUE value in one frame of Non_interlace mode or SECOND field of Interlace mode. D7-0 CALVAL_G[23:16]
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Auto Calibration GREEN Value - Byte 3 (Address 3Bh) (RO) It states the byte 3 of the number of Phase Calibration GREEN value in one frame. D7-6 D5-0 Reserved CALVAL_G[29:24]
Auto Calibration BLUE Value - Byte 0 (Address 3Ch) (RO) It states the byte 0 of the number of Phase Calibration BLUE value in one frame or the byte 0 of the number of Histogram BLUE value in one frame or the MIN/MAX RED value in one frame. D7-0 CALVAL_B[7:0]
Auto Calibration BLUE Value - Byte 1 (Address 3Dh) (RO) It states the byte 1 of the number of Phase Calibration BLUE value in one frame or the byte 1 of the number of Histogram BLUE value in one frame or the MIN/MAX GREEN value in one frame. D7-0 CALVAL_B[15:8]
Auto Calibration BLUE Value - Byte 2 (Address 3Eh) (RO) It states the byte 2 of the number of Phase Calibration BLUE value in one frame or the byte 2 of the number of Histogram BLUE value in one frame or the MIN/MAX BLUE value in one frame. D7-0 CALVAL_B[23:16]
Auto Calibration BLUE Value - Byte 3 (Address 3Fh) (RO) It states the byte 3 of the number of Phase Calibration BLUE value in one frame. D7-6 D5-0 Reserved CALVAL_B[29:24]
Pixel Grab V Reference Position - Low (Address 40h) (R/W) It states the low byte of Vertical Reference Position in Pixel Grab Mode. D7-0 VGRAB_POS[7:0]
Pixel Grab V Reference Position - High (Address 41h) (R/W) It states the high byte of Vertical Reference Position in Pixel Grab Mode. D7-3 D2-0 Reserved VGRAB_POS[10:8]
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MTL007
Pixel Grab H Reference Position - Low (Address 42h) (R/W) It states the low byte of Horizontal Reference Position in Pixel Grab Mode. D7-0 HGRAB_POS[7:0]
Pixel Grab H Reference Position - High (Address 43h) (R/W) It states the high byte of Horizontal Reference Position in Pixel Grab Mode. D7-3 D2-0 Reserved HGRAB_POS[10:8]
Histogram Reference Color - RED (Address 44h) (R/W) It states the Histogram Reference RED Color in Histogram Mode. D7-0 HIST_R[7:0]
Histogram Reference Color - GREEN (Address 45h) (R/W) It states the Histogram Reference GREEN Color in Histogram Mode. D7-0 HIST_G[7:0]
Histogram Reference Color - BLUE (Address 46h) (R/W) It states the Histogram Reference BLUE Color in Histogram Mode. D7-0 HIST_B[7:0]
SYNC Processor Control (Address 48h) (R/W) D7-2 D1-0 Reserved SYNC Source 00: from H/V SYNC; 01: from CVSYNC (Composite SYNC); 1x: Auto switch to CVSYNC when CVSYNC is present, but VSYNC not.
Auto Position Control (Address 49h) (R/W) D7-2 D1 Reserved Auto Position Burst Mode Enable 0: Single Mode; 1: Burst Mode Auto Position Enable (W) 0: Disable; 1: Enable
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D0
MTL007
Auto Position Ready Flag (R) 0: Ready; 1: Not Ready
Auto Position Reference Color - RED (Address 4Ah) (R/W) It defines the red component color for selecting between black and non-black pixels. D7-0 REF_COLOR_RED[7:0]
Auto Position Reference Color - GREEN (Address 4Bh) (R/W) It defines the green component color for selecting between black and non-black pixels. D7-0 REF_COLOR_GREEN[7:0]
Auto Position Reference Color - BLUE (Address 4Ch) (R/W) It defines the blue component color for selecting between black and non-black pixels. D7-0 REF_COLOR_BLUE[7:0]
Clamp Pulse Control 0 (Address 4Eh) (R/W) D7 Clamp Pulse Mask 0: Normal; 1: Mask out Clamp Pulse Clamp Pulse Start Reference Edge 0: From Input HSYNC trailing edge; 1: From Input HSYNC leading edge Clamp Pulse output Polarity 0: Active High; 1: Active Low Clamp Pulse Start Start of Clamp Pulse after the selected edge of Input HSYNC by Input DCLK.
D6
D5
D4-0
Clamp Pulse Control 1 (Address 4Fh) (R/W) D7 Clock Source for Clamp Pulse Generation; 0: from Input clock, IDCLK; 1: from OSC clock, REFCLK Reserved Clamp Pulse Width; To Adjust Clamp Pulse Width by Input DCLK.
D6-5 D4-0
Input VS Period Count by REFCLK - Low (Address 50h) (RO)
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MTL007
It states the low byte of the number of REFCLK of the Vertical Sync period measurement. D7-0 VSPRD[7:0]
Input VS Period Count by REFCLK - High (Address 51h) (RO) It states the high byte of the number of REFCLK of the Vertical Sync period measurement. D7-4 D3-0 Reserved VSPRD[11:8]
Input V Back Porch Count by Input HS - Low (Address 52h) (RO) It states the low byte of the number of lines between the end of VSYNC and the active image. D7-0 VBPW[7:0]
Input V Back Porch Count by Input HS - High (Address 53h) (RO) It states the high byte of the number of lines between the end of VSYNC and the active image D7-3 D2-0 Reserved VBPW[10:8]
Input V Active Image Count by Input HS - Low (Address 54h) (RO) It states the low byte of the number of the active image lines. D7-0 VACTW[7:0]
Input V Active Image Count by Input HS - High (Address 55h) (RO) It states the high byte of the number of the active image lines D7-3 D2-0 Reserved VACTW[10:8]
Input V Total Image Count by Input HS - Low (Address 56h) (RO) It states the low byte of the number of the total image lines. D7-0 VTOTW[7:0]
Input V Total Image Count by Input HS - High (Address 57h) (RO) It states the high byte of the number of the total image lines. D7-3 Reserved
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MTL007
D2-0 VTOTW[10:8]
Input HS Period Count by REFCLK - Low (Address 58h) (RO) It states the low byte of the number of REFCLKs of the Horizontal Sync period measurement. D7-0 HSPRD[7:0]
Input HS Period Count by REFCLK - High (Address 59h) (RO) It states the high byte of the number of REFCLKs of the Horizontal Sync period measurement. D7-5 D4-0 Reserved HSPRD[12:8]
Input H Back Porch Count by Input Pixel Clock -Low (Address 5Ah) (RO) It states the low byte of the number of pixels between the end of HSYNC and the active image. D7-0 HBPW[7:0]
Input H Back Porch Count by Input Pixel Clock -High (Address 5Bh) (RO) It states the high byte of the number of pixels between the end of HSYNC and the active image. D7-3 D2-0 Reserved HBPW[10:8]
Input H Active Image Count by Input Pixel Clock-Low(Address 5Ch) (RO) It states the low byte of the number of the Horizontal active image pixels. D7-0 HACTW[7:0]
Input H Active Image Count by Input Pixel Clock-High(Address 5Dh)(RO) It states the high byte of the number of the Horizontal active image pixels. D7-3 D2-0 Reserved HACTW[10:8]
Input H Total Image Count by Input Pixel Clock- Low (Address 5Eh) (RO) It states the low byte of the number of the Horizontal total image pixels. D7-0 HTOTW[7:0]
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MTL007
Input H Total Image Count by Input Pixel Clock- High (Address 5Fh) (RO) It states the high byte of the number of the Horizontal total image pixels. D7-3 D2-0 Reserved HTOTW[10:8]
Display Vertical Total - Low (Address 60h) (R/W) It defines the low byte of the number of lines per display frame. D7-0 DV_TOTAL[7:0]
Display Vertical Total - High (Address 61h) (R/W) It defines the high byte of the number of lines per display frame. D7-3 D2-0 Reserved DV_TOTAL[10:8]
Display Vertical SYNC End - Low (Address 62h) (R/W) It defines the low byte of Vertical SYNC end position in lines. D7-0 DV_SYNC_END[7:0]
Display Vertical SYNC End - High (Address 63h) (R/W) It defines the high byte of Vertical SYNC end position in lines. D7-3 D2-0 Reserved DV_SYNC_END[10:8]
Note: Display Vertical SYNC Start is always equal 0.
Display Vertical Active Start - Low (Address 64h) (R/W) It defines the low byte of Vertical Active region start position in lines. D7-0 DV_ACT_START[7:0]
Display Vertical Active Start - High (Address 65h) (R/W) It defines the high byte of Vertical Active region start position in lines. D7-3 D2-0 Reserved DV_ACT_START[10:8]
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MTL007
Display Vertical Active End - Low (Address 66h) (R/W) It defines the low byte of Vertical Active region end position in lines. D7-0 DV_ACT_END[7:0]
Display Vertical Active End - High (Address 67h) (R/W) It defines the high byte of Vertical Active region end position in lines. D7-3 D2-0 Reserved DV_ACT_END[10:8]
*Display Vertical Border Start - Low (Address 68h) (R/W) It defines the low byte of Vertical Border start position in lines. D7-0 DV_BOR_START[7:0]
*Display Vertical Border Start - High (Address 69h) (R/W) It defines the high byte of Vertical Border start position in lines. D7-3 D2-0 Reserved DV_BOR_START[10:8]
*Display Vertical Border End - Low (Address 6Ah) (R/W) It defines the low byte of Vertical Border end position in lines. D7-0 DV_BOR_END[7:0]
*Display Vertical Border End - High (Address 6Bh) (R/W) It defines the high byte of Vertical Border end position in lines. D7-3 D2-0 Reserved DV_BOR_END[10:8]
Display Horizontal Total - Low (Address 70h) (R/W) It defines the low byte of the number of display clock cycles per display line. D7-0 DH_TOTAL[7:0]
Display Horizontal Total - High (Address 71h) (R/W) It defines the high byte of the number of display clock cycles per display line.
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MTL007
D7-3 D2-0 Reserved DH_TOTAL[10:8]
Display Horizontal SYNC End - Low (Address 72h) (R/W) It defines the low byte of Horizontal SYNC end position in display clock cycles. D7-0 DH_SYNC_END[7:0]
Display Horizontal SYNC End - High (Address 73h) (R/W) It defines the high byte of Horizontal SYNC end position in display clock cycles. D7-3 D2-0 Reserved DH_SYNC_END[10:8]
Note: Display Horizontal SYNC Start is always equal 0.
Display Horizontal Active Start - Low (Address 74h) (R/W) It defines the low byte of Horizontal Active region start position in display clock cycles. D7-0 DH_ACT_START[7:0]
Display Horizontal Active Start - High (Address 75h) (R/W) It defines the high byte of Horizontal Active region start position in display clock cycles. D7-3 D2-0 Reserved DH_ACT_START[10:8]
Display Horizontal Active End - Low (Address 76h) (R/W) It defines the low byte of Horizontal Active region end position in display clock cycles. D7-0 DH_ACT_END[7:0]
Display Horizontal Active End - High (Address 77h) (R/W) It defines the high byte of Horizontal Active region end position in display clock cycles. D7-3 D2-0 Reserved DH_ACT_END[10:8]
*Display Horizontal Border Start - Low (Address 78h) (R/W) It defines the low byte of Horizontal Border start position in display clock cycles.
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MTL007
D7-0 DH_BOR_START[7:0]
*Display Horizontal Border Start - High (Address 79h) (R/W) It defines the high byte of Horizontal Border start position in display clock cycles. D7-3 D2-0 Reserved DH_BOR_START[10:8]
*Display Horizontal Border End - Low (Address 7Ah) (R/W) It defines the low byte of Horizontal Border end position in display clock cycles. D7-0 DH_BOR_END[7:0]
*Display Horizontal Border End - High (Address 7Bh) (R/W) It defines the high byte of Horizontal Border end position in display clock cycles. *D7 Auto-period Enable 0: Disable; 1: Enable Reserved DH_BOR_END[10:8]
D6-3 *D2-0
*NFB Timing Load Value (Address 7Eh) It defines the low byte of NFB Horizontal Counter load value. The total additive(positive number)/subtractive(negative number) pixels in one frame. It is 2's complement value. *D7-0 DH_NFB_LD_VAL[7:0]
NFB Timing Control (Address 7Fh) It defines the NFB timing setting and high byte of NFB Horizontal Counter load value. D7 Free Running mode Select 0: Normal; 1: Free Running NFB Synchronization mode 000: Delay mode. Output HSYNC trimmed in output VSYNC and VDE issued on next HSYNC when Lock event occurs; 010: Immediate mode. Output HSYNC trimmed immediately and VDE issued on next HSYNC when Lock event occurs; 110: Early mode. Output HSYNC trimmed immediately and VDE issued immediately when Lock event occurs.
D6-4
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*D3-0 DH_NFB_LD_VAL[11:8]
Output Image Control Register 0 (Address 88h) (R/W) D7-5 RGB Sharpness Factor Select 000: Disable; 001: 1/16; 010: 2/16; 011: 3/16; 100: 4/16; 101: 5/16; 110: 6/16; 111: 8/16 OUTPUT port MSB / LSB change 0: No Exchange; 1: Exchange Auto Black Enable 0: Disable; 1: Enable Output Pixel 18 bit RGB Mode Select 0: 24 bit RGB; 1: 18 bit RGB Output Dual Pixel Data Exchange 0: Normal; 1: Exchange Reserved // Output Dual Pixel Select; //0: Dual Pixel; //1: Single Pixel
D4
D3
D2
D1
D0
Output Image Control Register 1 (Address 89h) (R/W) D7 RGB Smooth Control Enable 0: Disable; 1: Enable Reserved RGB Brightness Control Enable 0: Disable; 1: Enable RGB Gain Control Enable 0: Disable; 1: Enable Pattern Generation Type Select 00: Single Color; 01: Vertical Line Moire; 10: Horizontal Line Moire; 11: Dot Moire
D6 D5
D4
D3-2
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*D1 Border Window Function (Only valid in Free Running mode Reg. 7Fh/D7=1) 0: OFF; 1: ON Output Blank Screen 0: Normal; 1: Output Pixel masked as BLACK color
D0
Output Image Control Register 2 (Address 8Ah) (R/W) D7 D6 Reserved Temporal Dithering Enable 0: Static Dithering; 1: Temporal Dithering Reserved Dithering Enable; 0: Disable; 1: Enable Color Gain Control Resolution Select 0: 8-bit Resolution; 1: 9-bit Resolution 8-bit or 10-bit Gamma Table 0: 8-bit; 1: 10-bit Gamma Table R/W Access Enable 0: Disable; 1: Enable
D5 D4
D3
D2
D1
D0
Gamma Correction Function 0: OFF; 1: ON
Color Gain Control - RED (Address 90h) (R/W) It can be used to adjust the gain of RED component of the Display Image. D7-0 RGAIN[7:0] 0(00h) ~ x1(80h) ~ x1.992185(FFh)
Color Gain Control - GREEN (Address 91h) (R/W) It can be used to adjust the gain of GREEN component of the Display Image. D7-0 GGAIN[7:0] 0(00h) ~ x1(80h) ~ x1.992185(FFh)
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Color Gain Control - BLUE (Address 92h) (R/W) It can be used to adjust the gain of BLUE component of the Display Image. D7-0 BGAIN[7:0] 0(00h) ~ x1(80h) ~ x1.992185(FFh)
Color Brightness Control - RED (Address 93h) (R/W) It can be used to adjust the brightness of RED component of the Display Image. D7-0 RBRIGHT[7:0] -128(80h) ~ 0(00h) ~127(7Fh)
Color Brightness Control - GREEN (Address 94h) (R/W) It can be used to adjust the brightness of GREEN component of the Display Image. D7-0 GBRIGHT[7:0] -128(80h) ~ 0(00h) ~127(7Fh)
Color Brightness Control - BLUE (Address 95h) (R/W) It can be used to adjust the brightness of BLUE component of the Display Image. D7-0 BBRIGHT[7:0] -128(80h) ~ 0(00h) ~127(7Fh)
*Border Window Color - RED (Address 96h) (R/W) When the Display Image is not expanded to full screen, it can be specified as the RED component of the border color. D7-0 BCR[7:0]
*Border Window Color - GREEN (Address 97h) (R/W) When the Display Image is not expanded to full screen, it can be specified as the GREEN component of the border color. D7-0 BCG[7:0]
*Border Window Color - BLUE (Address 98h) (R/W) When the Display Image is not expanded to full screen, it can be specified as the BLUE component of the border color. D7-0 BCB[7:0]
*Dithering Table Data Port (Address 9Eh) (R/W)
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Since the Dithering Table is downloadable, this data port is the entry address. D7-0 DITHER_REG[7:0]
Gamma Table Data Port (Address 9Fh) (R/W) Since the Gamma Table is downloadable, this data port is the entry address. D7-0 GAMMA_PORT[7:0]
OSD Control Registers 0 (Address A0h) (R/W) D7 OSD Output Clock Select 0: from Internal Display Dot Clock; 1: from Internal Display Dot Clock x 2 OSD Output VS Invert 0: Normal; 1: Invert OSD Output VS Select 00: Display VDE, when Reg. 89h/D1=0; Display VBDE, when Reg. 89h/D1=1; 01: Display VS; 1x: Input VS OSD Function 0: OFF; 1: ON Reserved OSD TYPE Select 00: OSDRGB = {R0000000, G0000000, B0000000}; 01: OSDRGB = {RR000000, GG000000, BB000000}; 10: OSDRGB = {RRRR0000, GGGG0000, BBBB0000}; 11: OSDRGB = {RRRRRRRR, GGGGGGGG, BBBBBBBB}; R = OSDR, G = OSDG, B = OSDB
D6
*D5-4
D3
D2 D1-0
OSD Control Register 1 (Address A1h) (R/W) D7 OSD Output HS Invert; 0: Normal; 1: Invert. OSD Output DCLK Invert; 0: Normal; 1: Invert. OSD Output HS Delay 4 steps to change, each of them is 1ns delay/step. OSD Input Data Sample Clock Invert 0: Normal; 1: Invert.
D6
D5-4 D3
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D2-0 OSD Input Data Sample Clock Delay 8 steps to change, each of them is 1ns delay/step.
OSD Control Register 2 (Address A2h) (R/W) D7-4 D3-0 Reserved OSD Output Clock Delay 16 steps to change, each of them is 1ns delay/step.
OSD Control Register 3 (Address A3h) (R/W) D7 OSD Intensity Pulse Polarity Invert 0: Disable; 1: Enable Reserved OSD Transparent Control Enable 0: Disable; 1: Enable OSD Weighting Control Enable 0: Disable; 1: Enable OSD Weighting Factor (N) Select N = 0 ~ 15 (D [3:0] = 0000 ~ 1111) RGB Weighting Factor = (N+1)/16; D4=0: OSD Weighting Factor = 1; D4=1: OSD Weighting Factor = (15-N)/16
D6 D5
D4
D3-0
Output Invert Control (Address A4h) (R/W) D7 D6 Reserved RGB Data Invert Enable 0: Disable; 1: Enable Display DCLKH Invert 0: Normal; 1: Invert Display DCLK Invert 0: Normal; 1: Invert Reserved Display Data Enable (DDEN) Invert 0: Normal; 1: Invert Display VSYNC Invert 0: Normal;
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D5
D4
D3 D2
D1
MTL007
1: Invert D0 Display HSYNC Invert 0: Normal; 1: Invert
Output Tri_state Control (Address A5h) (R/W) D7 Display Data R2OUT, G2OUT, B2OUT Output Disable 0: Normal; 1: Tri_stated Display Data R1OUT, G1OUT, B1OUT Output Disable 0: Normal; 1: Tri_stated Display DCLKH Output Disable 0: Normal; 1: Tri_stated Display DCLK / Display VSYNC / Display HSYNC / Display data enable Output Disable 0: Normal; 1: Tri_stated OSD OCLK / OVSYNC / OHSYNC Output Disable 0: Normal; 1: Tri_stated Reserved
D6
D5
D4
D3
D2-D0
Output Clocks Delay Adjustment (Address A6h) (R/W) D7-4 D3-0 Display DCLKH delay adjustment 16 steps to adjust, Typical 1ns delay/step Display DCLK delay adjustment 16 steps to adjust, Typical 1ns delay/step
Output Clocks Duty Cycle Adjustment (Address A7h) (R/W) D7 Display DCLKH duty cycle Increase/Decrease 0: Decrease; 1: Increase Display DCLKH duty cycle adjustment 8 steps to adjust, Typical 0.5ns delay/step Display DCLK duty cycle Increase/Decrease 0: Decrease; 1: Increase Display DCLK duty cycle adjustment 8 steps to adjust, Typical 0.5ns delay/step
D6-4 D3
D2-0
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*Display Line Buffer Data Sample Adjustment (Address A8h) (R/W) *D7 Reg. AEh, AFh Selection 0: Report Output Horizontal Total Residue Number; 1: Report Output Vertical Total Counter Value Reserved Display Vsync Mode 0: Normal; 1: Delay 1 clock Reserved
D6 *D5
D4-0
Output Miscellaneous Control (Address A9h) (R/W) D7 Second field Line Buffer Overflow status for Interlace input (RO) 0: Not Overflow; 1: Overflow Second field Line Buffer Underflow status for Interlace input (RO) 0: Not Underflow; 1: Underflow First field Line Buffer Overflow status for Interlace input or Line buffer Overflow status for Non-interlace input (RO) 0: Not Overflow; 1: Overflow First field Line Buffer Underflow status for Interlace input or Line Buffer Overflow status for Non-interlace input (RO) 0: Not Underflow; 1: Underflow Auto Output Horizontal Total Calculation Start (W) 0: Disable; 1: Enable Auto Output Horizontal Total Calculation Ready Flag (R) 0: Ready; 1: Not Ready *D2-0 Internal VOU Debug Bus Select
D6
D5
D4
D3
Output Vertical Active Line Number - Low (Address AAh) (R/W) It defines the low byte of Output Vertical Active Line Number -1, only used for getting the values of Reg. ACh and ADh. D7-0 OVDE[7:0]
Output Vertical Active Line Number - High (Address ABh) (R/W) It defines the high byte of Output Vertical Active Line Number -1, only used for getting the values of Reg. ACh and ADh.
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D2-0 OVDE[10:8]
Output Horizontal Total Pixel Number - Low (Address ACh) (RO) It states the low byte of Output Horizontal Total Pixel Number. D7-0 OHTOT[7:0]
Output Horizontal Total Pixel Number - High (Address ADh) (RO) It states the high byte of Output Horizontal Total Pixel Number, or output vertical total counter value, setting by RegA8[7]. D2-0 OHTOT[10:8]
Output Horizontal Total Residue Number - Low (Address AEh) (RO) It states the low byte of Output Horizontal Total Pixel Residue Number, or output vertical total counter value, setting by RegA8[7]. D7-0 OHTOT_RES[7:0]
Output Horizontal Total Residue Number - High (Address AFh) (RO) It states the high byte of Output Horizontal Total Pixel Residue Number. D7-2 D2-0 Reserved OHTOT_RES[10:8]
Zoom Control Register 0 (Address B0h) (R/W) D7 D6-4 Reserved Vertical Scale Select 0xx: PASS mode; 10x: DUPLICATE mode; 110: BILINEAR mode; 111: INTERPOLATION TABLE mode (Down Scaling Mode: Enable Average the neighbor lines) Reserved Horizontal Scale Select 0xx: PASS mode; 10x: DUPLICATE mode; 110: BILINEAR mode; 111: INTERPOLATION TABLE mode
D3 D2-0
Zoom Control Register 1 (Address B1h) (R/W) D7-1 Reserved
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D0 Interpolation Table R/W Access Enable 0: Disable; 1: Enable
Zoom Vertical Scale Ratio - Low (Address B4h) (R/W) It defines the low byte of vertical scale ratio value for scale up. D7-0 ZVSF[7:0]
Zoom Vertical Scale Ratio - High (Address B5h) (R/W) It defines the high byte of vertical scale ratio value for scale up. D7-0 ZVSF[15:8]
ZVSF = CEIL[(input_height - 1)/ (output_height - 1)* 216]
Zoom Horizontal Scale Ratio - Low (Address B6h) (R/W) It defines the low byte of horizontal scale ratio value for scale up. D7-0 ZHSF[7:0]
Zoom Horizontal Scale Ratio - High (Address B7h) (R/W) It defines the high byte of horizontal scale ratio value for scale up. D7-0 ZHSF[15:8]
ZHSF = CEIL[(input_width - 1)/ (output_width - 1)* 216]
Interpolation Table Data Port (Address BFh) (R/W) It defines the entry address of the Interpolation table data port. D7-0 TFPORT[7:0]
Host Control Register 1 (Address C1h) (R/W) D7 D6 Reserved I2C Bus Address No Increment 0: Normal; 1: No Increment Double Buffer load Select 0: Immediately; 1: Delay to Display VSYNC Registers Double Buffer function Enable 0: Disable;
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D5
D4
MTL007
1: Enable D3-2 D1 D0 Reserved Display Registers Double Buffer Load (WO) Input Registers Double Buffer Load (WO)
*Host Fill RED Color (Address C6h) (R/W) It defines Fill Red color for Line Buffer Flush defined in Reg. 16h/D5. D7-0 HFR[7:0]
*Host Fill GREEN Color (Address C7h) (R/W) It defines Fill Green color for Line Buffer Flush defined in Reg. 16h/D5. D7-0 HFG[7:0]
*Host Fill BLUE Color (Address C8h) (R/W) It defines Fill Blue color for Line Buffer Flush defined in Reg. 16h/D5. D7-0 HFB[7:0]
Host Access Mode Status (Address CBh) (RO) D7-1 D0 Reserved Host Access Mode 0: 2-wire Serial mode (IIC); 1: 8-bit Parallel mode
Clock Synthesizer Control Register (Address E0h) (R/W) D7 External Display Clock Selection 0: External Display Clock 1; 1: External Display Clock 2 Reserved Internal Display Clock Select It is used for two purposes: one for better clock duty cycle, the other for lower frequency testing in Tester. 0: VCG DCLK; 1: VCG DCLK / 2 Reserved Display Clock Source 0: Internal Display Clock; 1: External Reference Clock
D6-5 *D4
D3 D2
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D1 D0 Reserved Display Clock Synthesizer Enable 0: Enable; 1: Disable
Clock Synthesizer Value Load (Address E1h) (WO) D7-1 D0 Reserved Display Clock Synthesizer Value Load (WO)
Display Clock Synthesizer N Value (Address E2h) (R/W) D7-0 Display Clock Synthesizer N value
Display Clock Synthesizer M Value (Address E3h) (R/W) D7-0 Display Clock Synthesizer M value
Clock Synthesizer R Value (Address E6h) (R/W)
*D7-4 D3-2 D1-0
PLL Test mode Control Reserved Display Clock Synthesizer R value 00: Not divided; 01: Divided by 2; 10: Divided by 4; 11: Divided by 8
SYNC Interrupt Flag Control (Address E8h) (R) It contains the status of SYNC Interrupts. D7 Display VSYNC Pulse Interrupt Status 0: No Display VSYNC pulse detected; 1: Any Display VSYNC pulse detected Input VSYNC Pulse Interrupt Status 0: No Input VSYNC pulse detected; 1: Any Input VSYNC pulse detected VSYNC Presence Change Status 0: No Change; 1: Change HSYNC Presence Change Status 0: No Change; 1: Change
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D6
D5
D4
MTL007
D3 VSYNC Polarity Change Status 0: No Change; 1: Change HSYNC Polarity Change Status 0: No Change; 1: Change VSYNC Frequency Change Status 0: No Change; 1: Change HSYNC Frequency Change Status 0: No Change; 1: Change
D2
D1
D0
SYNC Interrupt Flag Control (Address E8h) (W) It is used to clear the corresponding SYNC interrupt signal when Software finishes serving the interrupt service routine. D7 Clear Display VSYNC Pulse Interrupt Enable 0: Disable; 1: Enable Clear Input VSYNC Pulse Interrupt Enable 0: Disable; 1: Enable Clear VSYNC Presence Change Interrupt Enable 0: Disable; 1: Enable Clear HSYNC Presence Change Interrupt Enable 0: Disable; 1: Enable Clear VSYNC Polarity Change Interrupt Enable 0: Disable; 1: Enable Clear HSYNC Polarity Change Interrupt Enable 0: Disable; 1: Enable Clear VSYNC Frequency Change Interrupt Enable 0: Disable; 1: Enable Clear HSYNC Frequency Change Interrupt Enable 0: Disable; 1: Enable
D6
D5
D4
D3
D2
D1
D0
General Interrupt Flag Control (Address E9h) (R) It contains the status of General Interrupts.
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D7-2 D1 Reserved Auto Position Finish Status (valid for Single mode only) 0: Not Finished; 1: Finished Auto Calibration Finish Status (valid for Single mode only) 0: Not Finished; 1: Finished
D0
General Interrupt Flag Control (Address E9h) (W) It is used to clear the corresponding general interrupt signal when Software finishes serving the interrupt service routine. D7-2 D1 Reserved Clear Auto Position Finish Interrupt Enable 0: Disable; 1: Enable Clear Auto Calibration Finish Interrupt Enable 0: Disable; 1: Enable
D0
SYNC Interrupt Enable Control (Address EAh) (R/W) It is used to enable SYNC Interrupt function. D7 Display VSYNC Pulse Interrupt Enable 0: Disable; 1: Enable Input VSYNC Pulse Interrupt Enable 0: Disable; 1: Enable VSYNC Presence Change Interrupt Enable 0: Disable; 1: Enable HSYNC Presence Change Interrupt Enable 0: Disable; 1: Enable VSYNC Polarity Change Interrupt Enable 0: Disable; 1: Enable HSYNC Polarity Change Interrupt Enable 0: Disable; 1: Enable VSYNC Frequency Change Interrupt Enable 0: Disable; 1: Enable HSYNC Frequency Change Interrupt Enable
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D6
D5
D4
D3
D2
D1
D0
MTL007
0: Disable; 1: Enable
General Interrupt Enable Control (Address EBh) (R/W) It is used to enable General Interrupt functions. D7 Interrupt Output Polarity 0: Active High; 1: Active Low Reserved Auto Position Finish Interrupt Enable 0: Disable; 1: Enable Auto Calibration Finish Interrupt Enable 0: Disable; 1: Enable
D6-2 D1
D0
HS Frequency Change Interrupt Compare (Address ECh) (R/W) It is used to control Interrupt generation by comparing the frequency change value when Input HS Frequency changes. D7-0 HSCMPREG[7:0]
*Device/Revision ID (Address F0h) (RO) D7-4 D3-0 Device ID Revision ID
Power Management Control (Address F1h) (R/W) D7 D6 Reserved Power Down Gamma & Interpolation Table 0: Normal; 1: Power Down Reserved Power Down Line Buffers 0: Normal; 1: Power Down Regulator Power Down 0: Normal; 1: Power Down Mask REFCLK 0: Disable; 1: Enable
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D5 D4
D3
D2
MTL007
D1 Power Down all the clocks except REFCLK 0: Normal; 1: Power Down Software Reset Enable 0: Disable; 1: Enable
D0
*Line Buffer Self Test Control (Address F8h) (R/W) It controls the operation of Line Buffer Self Test Mode. D7-2 D1 Reserved Line Buffer Self Test mode Finish Status (RO) 0: Finish; 1: Not Finish Line Buffer Self Test mode Enable 0: Disable; 1: Enable
D0
*Line Buffer Self Test Result Status (Address F9h) (RO) It contains the status of Line Buffer Self Test Mode result. D7-5 D4 Reserved Line Buffer 4 Self Test mode Result Status (RO) 0: Success; 1: Fail Line Buffer 3 Self Test mode Result Status (RO) 0: Success; 1: Fail Line Buffer 2 Self Test mode Result Status (RO) 0: Success; 1: Fail Line Buffer 1 Self Test mode Result Status (RO) 0: Success; 1: Fail Line Buffer 0 Self Test mode Result Status (RO) 0: Success; 1: Fail
D3
D2
D1
D0
*Debug/Test Mode Control (Address FAh) (R/W) D7 *D6-4 D3-2 Reserved Internal Top Debug Bus Select Reserved
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*D1 VCG Test mode Enable 0: Disable; 1: Enable Debug mode Enable 0: Disable; 1: Enable
*D0
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ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS Recommended Operating Conditions Symbol Vcc Tamb Tstg Parameter Operation Voltage Operating Ambient Temperature Storage Temperature Min 3.0 0 -55 Typ 3.3 Max 3.6 70 150 Unit V
o o
C C
DC Electrical Characteristics for 3.3 V Operation Symbol VIL VIH VtVt+ VOL VOH RI ILI ILO Parameter Input Low Voltage Input High Voltage Input Schmitt Trigger Low Voltage at pins SDA and SCK Input Schmitt Trigger High Voltage at pins SDA and SCK Output Low Voltage Output High Voltage Input Pull-up/Down Resistance Input Leakage Current Output Leakage Current VIL = 0v or VIH = VCC -10 -20 2.4 75 10 20 2.0 1.0 1.7 0.4 V V Kohm uA uA Condition Min Typ Max 0.8 Unit V V
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MTL007
AC CHARACTERISTICS Input Interface Timing
IPCLK
Input VS/HS
Tivhs Tivhh
PIXIN[23:0]
Tids Tidh
Figure-11 Input Interface Timing
Table-1 Input Interface Timing Symbol Tids Tidh Tivhs Tivhh Parameter Input Image Signal Setup Time for IPCLK Input Image Signal Hold Time for IPCLK Input VSYNC/HSYNC Setup Time for IPCLK Input VSYNC/HSYNC Hold Time for IPCLK Min 2 3 2 3 Max Unit ns ns ns ns
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Output Interface Timing
DDCLK
Tdvs
Display VS
Tdhs
Display HS
Tdde
Display DDEN
Tddp
PIXOUT[23:0]
Figure-12 Output Interface Timing
Table-2 Output Interface Timing Symbol Tdvs Tdhs Tdde Tddp Parameter Display VSYNC Output Delay to DDCLK Display HSYNC Output Delay to DDCLK Display DDEN Output Delay to DDCLK Display Data Output Delay to DDCLK Min 2 0.5 1 1.5 Max Unit ns ns ns ns
Note: DDCLK phase can be adjusted relative to data and control outputs using the DDCLK_INV (Reg. A4h/D5-4) and DDCLK_DELAY[2:0] (Reg. A6h/D7-0) programming controls.
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MTL007
OSD Interface Timing
OCLK
Tosdd
OVSYNC / OHSYNC
Input OSDDEN / OSDRED / OSDGRN / OSDBLU
Tosds Tosdh
Figure-13 OSD Interface Timing
Table-3 OSD Interface Timing Symbol Tosdd Tosds Tosdh Parameter OSD VS / HS Output Delay to OCLK OSD Signal Input Setup Time for OCLK OSD Signal Input Hold Time for OCLK Min 2 5.5 0 Max Unit ns ns ns
Note: OCLK phase can be adjusted using OCLK_INV (Reg. A1h/D3) programming control and OHSYNC phase can be adjusted using OHSYNC_DELAY[1:0] (Reg. A1h/D5-4) programming control.
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MTL007
I2C Host Interface Timing
Thigh
Tsu:sta Tlow
Thd:sto
Thd:sta
Tsu:dat
Thd:dat
Tsu:sto
Figure-14 Host Interface Timing
Table-4 Host Interface Timing Symbol Thigh Tlow Tsu:dat Thd:dat Tsu:sta Thd:sta Tsu:sto Thd:sto Clock High Period Clock Low Period Data in Setup Time Data in Hold Time Start condition Setup Time Start condition Hold Time Stop condition Setup Time Stop condition Hold Time Parameter Min 500 500 200 100 500 500 500 500 Max Unit ns ns ns ns ns ns ns ns
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PACKAGE OUTLINE
Symbol
Dimension in Millimeters
Dimension in Inches
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Min A A1 A2 B C D D1 E E1 e L L1 y 0 0.73 0.25 2.73 0.17 0.09 23.70 19.90 17.70 13.90 Nom 2.85 0.22 23.90 20.00 17.90 14.00 0.50 BSC 0.88 1.95 BSC 0.10 7 0 1.03 0.029 Max 3.40 2.97 0.27 0.20 24.10 20.10 18.10 14.10 Min 0.010 0.107 0.007 0.004 0.933 0.783 0.697 0.547 Nom 0.112 0.009 0.941 0.787 0.705 0.551 0.020 BSC 0.035 0.077 BSC 0.004 7 0.041 Max 0.134 0.117 0.011 0.008 0.949 0.791 0.713 0.555
ORDERING INFORMATION Standard Configuration: Prefix MTL Part Type 007 Package Type F: PQFP
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